Samsung made headlines last week when it announced the availability of its newest 3D IC technology.
The new technology, called X-Cube, was tested and proven in a 7nm test chip, which stacked SRAM on top of a logic chip. The result was a smaller footprint and shorter signal paths, meaning faster signal propagation and less power consumption. X-Cube is also available in advanced nodes: both 7nm and 5nm.
Comparison in SoC, SiP, and SoB. Image used courtesy of Resve Salah et al.
This advance from Samsung addresses several trends in chip design: facing the end of Moore’s law, increasing chip functionality, and addressing the difficulties of systems-on-chip (SoCs).
The Issue With Increasing SoC Size
One of the major challenges in SoC design is the fact that integrating more functional blocks onto one chip requires significantly more chip area.
But the combination of greater chip area and subsequently smaller node sizes leads to a huge rise in interconnect parasitics. Longer wire lengths must be used to connect different blocks in a physically larger chip, which increases interconnect inductance.
Sources of delay based on feature size and interconnect length. Image used courtesy of Parag Gadarki
The increased parasitic impedance of interconnects has come with a slew of problems. Data movement energy—the energy consumed from the physical movement of data on-chip—becomes one of the largest sources of energy consumption.
Signal propagation delay is also negatively affected by increased wire length and